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MAX7000 series CPLD-based data acquisition system
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CPLD is a complex PLD, specifically those larger than 1000 or more integrated programmable logic devices. It consists of the array, or array, input buffer circuit, the output macro-cell composition, with high integration gate can be configured for a variety of input and output forms, multi-clock drive, containing ROM or FLASH (partial support in-system programming), can be encrypted, low voltage, low power consumption and support for mixed programming, and other prominent features. CPLD logic cells and a powerful, general logic can be realized in the unit, so its simple interconnection between the circuit delay is the total bus unit itself and set the delay (usually within a few nanoseconds to ten the number of nanoseconds ), and predictable. Therefore, more suitable CPLD logic complex, multi-input variable but relatively little demand for the trigger logic-based system. 2 MAX7000 series CPLD and Platform Introduction High-speed data acquisition system as special requirements, in many of the CPLD device, select the ALTERA's MAX family of devices. MAX family of high performance and high density is based on its advanced MAX (Multiple Array Matrix - Multiple Array Matrix) framework, so as to provide a very high speed applications the price. MAX7000 series also offers the industry's fastest programmable logic solutions. It is based on CMOS EEPROM technology, the minimum propagation delay is 3.5ns, can counter faster than 200MHz, and for high-density device provides a very wide choice, very suitable for high-speed design applications. The company's MAX plusII software is an easy to use development tools, and its friendly interface, high degree of integration, compatible with industry standards, support FLEXMAXACEX 1K and other products. Provided for university students and software, are functionally similar with the commercial version, available only in limited on-chip. The MAX7000 series of these advantages, the following design is based on MAX7000 series. 3 CPLD Application in the high-speed addressing General data collection required by the CPU will be A / D conversion result read, and then dump the memory chip, so that at least four machine cycles. If a machine cycle in accordance with generally 1μs, then the maximum sampling rate can only reach 250kHz, Juenan meet the needs of high-speed sampling. In this system, direct deposit to the sampling data in the cache RAM, and memory addressing is used ALTERA EPM7032LC44-6 constitute the company's address generator to complete. Signal can be written A / D conversion clock signal, subject to a series combination of frequency and logic can also be generated by a separate circuit or on the address generator. EPM7032LC44-6 constitute the basic principle is to address generator using cascaded 74 161 5 20-bit synchronous counter composed of the first 20 connected to the cache RAM chip-select line is used to switch the buffer memory group. CPU2 of P1.7 with the control count to allow end, asynchronous clear, the 20-bit address line output to keep pace. The specific implementation can use a text editor graphics editor input or the input method. Here are the VHDL language program.
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